1. Field of the Invention
This invention relates to a charge coupled semiconductor device and the method of manufacture therefor; and, more particularly, to a charge coupled device (hereinafter CCD) having two levels of gate electrodes and self-aligned implanted barriers.
2. Description of the Prior Art
W. S. Boyle and G. E. Smith describe the basic concept of charge coupled semiconductor devices in an article published in the Apr. 19, 1970 Bell System Technical Journal, page 587, entitled "Charge Coupled Semiconductor Devices." As described by Boyle and Smith, a charge coupled device consists of a metal-insulation-semiconductor (MIS) structure in which minority carriers are stored in a "spatially defined depletion region," also called "potential well" at the surface of the semiconductor material. The charge is moved along the surface by moving the potential minimum. A paper on page 593 of the same volume of the Bell System Technical Journal by Amelio, et al., entitled "Experimental Verification of the Charge Coupled Device Concept" described experiments carried out to demonstrate feasibility of the charge coupled device concept.
As discussed by Boyle and Smith, charge coupled devices are potentially useful as shift registers, delay lines, and in two dimensions, as imaging devices or display devices.
A CCD structure comprises a multiplicity of potential wells within a semiconductor substrate. The potential well is employed for storing, or accumulating, packets of charge. The accumulated packets of charge comprise carriers which are minority in relation to the conductivity type of the predominant impurity in the substrate containing the potential wells. In one embodiment, barriers are implanted periodically in the surface of the substrate in intervals which define the lateral extremities of the potential wells. The barriers make possible unidirectional flow of the charge packets. In some prior art CCD structures, the size of the implanted barriers, and the size of the potential well between adjacent barriers varies. This restricts the charge handling capabilities and the packing density of the CCD structure.
A need existed to develop a process and a CCD structure that would have self alignment features which would permit the gate electrodes of the two phase CCD to be in substantial self alignment with the implanted barrier regions cooperatively coupled to the overlying gate electrodes. Also, a need existed for a process and a resultant CCD structure that would provide uniformity of implanted barrier size, and uniformity of potential well size. In addition, it is desirable that this process be compatible with large scale integration processing techniques for MOS circuits.
The importance of extremely accurate processing to yield devices with predictable, reproducible characteristics in charge coupled devices for use in two-phase operation was pointed out in one of the first papers on the subject, an article by Krambeck, Walden and Pickar entitled "Implanted Barrier Two-Phase Charge-Coupled Device" published in Applied Physics Letters, Vol. 19, No. 12, pp. 520-522, in 1971.
In Patent Application Ser. No. 429,329, filed Dec. 28, 1973 by M. P. Anthony, et al., entitled "Self Aligned CCD Element Including Fabrication Method Therefor," and assigned in common with the present application, a charge coupled semiconductor device having self-aligned implanted barriers and the process for making such a device is described.
Also, in a patent application Ser. No. 445,361 by G. F. Amelio et al. entitled "Method for Manufacturing a Charge Coupled Device Having Self-Aligned Implanted Barriers with Narrow Gaps Between Electrodes," and assigned in common with the present application, an improved method of manufacturing a CCD is disclosed in which the implanted barrier regions are self-aligned with corresponding edges of the gate electrodes and in which the gaps between the electrodes are relatively narrow.
As pointed out in the above-cited Anthony, et al., copending patent application, efficient CCD operation is hindered when sizable gaps exist between adjacent electrodes. These gaps are wasteful in that they consume material which could be used for other portions of the structure. Also, these gaps are undesirable since they must be passivated during operation.
In U.S. Pat. No. 3,756,924 entitled "Method of Fabricating a Semiconductor Device" by D. R. Collins, et al., a method for forming a structure having adjacent closely spaced electrodes is disclosed. The disclosed structure and method in this patent is distinct from the structure and method disclosed in this application, as will be shown in greater detail hereinbelow.
This invention provides a structure and process for fabricating a CCD in which the barrier regions are intrinsically aligned with corresponding two-phase electrodes which are separated by very narrow gaps, which process is compatible with isoplanar processing. The term "isoplanar," as used herein, refers to the isolation of integrated circuits by means of a first dielectric formed after gate oxidation is carried out in regions defined by a second dielectric layer.